Fast data transmission technologies (in particular optical) are being deployed on an unprecedented scale in the LHC era experiments. Fore-coming experiments require a new generation of data acquisition systems that are cost-effective and maximize the use of commercially available components. Using standard networking protocols and hardware will ensure compatibility between different components of the detectors, whilst allowing for seamless incremental upgrades to individual systems. Whilst the use of some application-specific devices is inevitable, it is highly desirable to use commercial networking devices and protocols as much as possible. One possible option would be the use of 1 and 10 Gigabit Ethernet. In particular, since much of the front-end electronics is actually and likely will be controlled by Field Programmable Gate Arrays (FPGA), it is vital to assess the suitability of FPGAs for directly driving network traffic and to optimize the performance of the hardware and protocols used to send the data over the network. The growing convergence of storage protocols (iScsi, FibreChannel over Ethernet,iWarp, RDMA), around 10 Gigabit Ethernet standard makes it attractive for deployment in new data acquisition systems. Event building would benefit from Remote Direct Memory Access. The RDMA/TCP specification enables 10 Gigabit Ethernet RDMA implementation at the physical layer and TCP/IP as the transport, combining the performance and latency advantages of RDMA with a low-cost, standards-based solution. The specification is intended to be implemented in hardware, on top of a so called TCP Offload Engine (TOE), a technology used in network interface cards to offload processing of the entire TCP/IP stack to the network controller. An FPGA driven 10 Gigabit Ethernet Media Access Controller(MAC) injects data via a 10 Gb/s Ethernet switch into a PC server farm for event building purposes. The FPGA emulates the synchronous interface of a generic experiment readout system. The emulator lends itself to test different approaches to data injection; besides the complex programming model of RDMA with a full-featured TCP transport, It makes sense to investigate a custom developed TCP stack to be embedded in a field programmable gate array. The effectiveness of this custom built TCP stack in an FPGA is to be tested on its own and against a traffic shaping mechanism. The testbed allows investigations of latency, throughput, buffering schemes and global event building bandwidth, but allows also the evaluation of novel schemes of traffic shaping based on the new IEEE extensions concerning virtual links and per link congestion signaling driven by hardware.