SOIPD is an R&D collaboration between the Padova Section of INFN, the Lawrence Berkeley National Laboratory (LBNL, Berkeley, USA) and UC Santa Cruz (UCSC, USA).
The purpose of this research activity is the fabrication of Monolithic Pixel Sensors in Silicon On Insulator Technology (SOI). SOI technology gives several advantages over the standard bulk CMOS approach: the small active volume and the lower junction capacitance allow designs with higher speed and lower power consumption; passive isolation gives higher latch-up immunity. A commercial deep-submicron SOI CMOS process by OKI, coupled with high-resistivity silicon substrates, was recently made available through KEK (Japan).
SOI technology allows the integration of CMOS electronics on a thin silicon layer which is electrically insulated from the wafer substrate by means of a thin buried oxide layer (BOX). Being the electronics insulated from the substrate, it becomes possible to use high resistivity substrate as sensitive volume for charged particle detection and imaging applications. Vias etched through the oxide contact the substrate from the electronics layer, so that pixel implants can be contacted and a reverse bias can be applied. The possibility to deplete the sensor layer greatly improves the charge collection efficiency.
In the framework of the collaboration between the University and INFN of Padova (Italy) and LBNL (USA), in 2007-2008 the first two prototype chips (LDRD-SOI-1 and LDRD-SOI-2), featuring a matrix of both analog and digital pixels, have been built and characterized.
Together with the detection of the first particles in the SOI pixels, one of the main challenges for the further development of the technology appeared. The bias applied to the high-resistivity substrate induces a potential below the CMOS electronics layer which is shielded only in part by the BOX. This potential acts as a backgate to the transistors shifting their thresholds. As a result of this “backgating” effect, the charge sensing and read-out electronics could only be operated for low to moderate depletion voltages Vd, up to 15–20 V, and thus the charge was collected by a depleted region of modest thickness, 25-50um, depending on the handle wafer resistivity. In these first prototype sensors a series of guard-rings was used to counter the back-gating effect.

At the beginning of 2009, a third chip (SOImager) has been delivered. It has been built in the OKI 0.20µm FD-SOI process, optimized for low leakage current. The CMOS circuitry is implanted on a 40nm Si layer on top of a 200nm thick buried oxide (BOX); the thickness of the CMOS layer is small enough for the layer to be fully depleted. The sensor has a 350μm thick high-resistivity (700 Ohm•cm) substrate. It consists of an array of 256x256 analog pixels (13.75µm pitch), readout by 4 parallel analog outputs (64×256 each) up to 50 MHz (328µs integration time, corresponding to ~ 2-3kframe/sec). It has an active area of 3.2×3.2 mm2. To limit the back-gate effect, a floating p-type guard-ring has been implemented around each pixel in the active area of the test chip. A series of floating and grounded guard-rings has also been implemented around the pixel matrix and around the peripheral I/O electronics. Both the pixel layout (3T-like architecture) and the guard ring configurations are the same as the LDRD-SOI-2 chip. The simple architecture intended to reproduce the good performance of LDRD-SOI-2 analog pixels on a “sizeable” active area.

Guard-rings take considerable space in the pixel and are only partially effective. Instead, the implant of a buried p-well (BPW) beneath the BOX and the transistors has been found to successfully screen the potential applied to the high-resistivity layer in single transistor test structures. This motivates the adoption of a BPW in the design of pixel cells immune from back-gating.

The following prototype chip, named “SOImager-2”, produced in 2010, derives its global architecture from the earlier “SOImager” chip. The sensitive area is a 3.5×3.5 mm2 matrix of 256×256 pixels arrayed on a 13.75um source pitch. In order to increase the speed of the serial read-out, the pixel matrix is divided into four parallel arrays of 64 columns each. Each array is connected to four identical parallel output analog stages. Guard-rings are implemented around the pixel matrix (p+ I/O) and the peripheral I/O electronics (p+ Outer) in order to insulate the transistors from the effect of the potential below the BOX. In order to optimize the design of the pixel cell for mitigating the back-gating effect and enhancing the charge collection, pixel cells of different design are implemented. The pixel cell keeps the same 3 T design of the earlier prototype for the whole matrix, but the pixel array is now divided into eight different 64×128 pixel sectors, each implementing a different layout. These layouts explore different diode sizes, configurations of floating and grounded guard-rings around the pixel, as well as the use of a buried p-well (BPW). This chip has been extensively characterized with short IR laser pulses, X-rays and on a CERN SPS beam-line with 200 GeV π-. This chip has been thinned down to 70um thickness in 2011 to allow full depletion; tests were performed with soft X-rays and 300 GeV π-.
Since 2012 the experiment is no longer funded by the INFN, but the group is still working to finalize the goals of the project.
In 2012 a new, larger chip, has been designed and submitted to the foundry (SOImager-3). It consists of an array of 512x320 pixels (13.75um of pitch),with a serial readout. The chip has been produced both on the standard N-type CZ substrate (nominal resistivity 700 Ohm-cm) and on novel High Resistivity Float Zone (FZ) substrates, both N-type (7 kOhm-cm) and P-Type (25 kOhm-cm). Unfortunately the leakage current of the new FZ substrates (not yet fully detector grade), coupled to the long integration time required to readout such a large number of pixels, prevented us to operate the devices properly, due to the early saturation of the matrix.
We are collaborating with the foundry in order to solve the problem of the quality of the substrates. Two orders to the foundry and to SCIPP (UCSC) are still pending, waiting for a final production.