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  TO-ASIC EXPERIMENT, RESPONSIBLE: Nunzio Randazzo    

To_asIC (Toward advanced sub micron IC)

The To_asIC proposal aims to acquire and maintain ultra-deep submicron, 90,65 and 45 nm, VSLI integration technology know-how.

The initiative is supported by groups, involved in the VLSI project, from Cagliari, Catania, Napoli, Perugia and Lecce. In recent years, the proposers have already gained experience in VLSI projects such as analog front-end electronics (CA-CT-PG), digital implementation of data transmission and processing (NA-CA) and in building "electronic detectors" (PG). All the projects were developed under the auspices of the INFN in line with the interests of the Institute.
The proposers’ idea is to maintain and develop the capacities acquired in this field, for future application in the Institute’s experimental activities, bearing in mind that the development of integrated electronics is of increasing importance for the building of detectors.

The ITRS (International Technology Roadmap for Semiconductors – http://www.itrs.net) predicts that within a few years VLSI development will see a migration from the 90 nm technological node downwards The passage to this state-of-art technology will not involve a simple redesigning of previously used circuits. It means learning new design flows that include sophisticated analyses of on-chip xtalk, SSONoise electro-migration, and IR-drop, just to name the most obvious. Process yield analysis techniques will also be necessary, based on a study of masks and lithographic processes and, last but not least, a low-power design approach and an evaluation of the various components of power consumption, including the quiescent components that are so important to ultra-deep technologies.
Obviously, all the above will be applied to the dual form par excellence: analog-digital.

In this context the Europractice consortium (with which the proposers collaborate), set up by the EU Seventh Research Framework Programme, has launched the IDESA training programme (http://www.idesa-training.org/) aimed at people from both the academic world and those researching ultra deep submicron technology.
The advantage of adhering to this initiative is that, besides the training, Europractice offers the possibility of low cost foundry runs thus freeing users from dependence on other channels that require dedicated runs and higher relative costs.


 GOALS OF TO-ASIC EXPERIMENT  
To_asIC (Toward advanced sub micron IC)

The To_asiC proposal aims to acquire and maintain ultra-deep submicron, 90,65 and 45 nm, VSLI integration technology know-how.

 

Istituto Nazionale di Fisica Nucleare - Piazza dei Caprettari, 70 - 00186 Roma
tel. +39 066840031 - fax +39 0668307924 - email: presidenza@presid.infn.it

F.M. F.E.