Future high energy physics experiments at Super B-Factory, SLHC and ILC put severe requirements to tracking systems, which will have to operate at high data rate with a minimum material budget. Innermost (and most critical) layers of tracking and vertexing detector systems will be mostly based on pixel sensors with a small pitch (≤ 20 um for ILC, ≤ 50 um for SuperB). These sensors, along with the readout electronics, will be required to have a high degree of radiation tolerance, a large signal-to-noise ratio and a high rate sparsified readout architecture yielding an advanced trigger information. The VIPIX project intends to build thin trackers demonstrators based on pixel sensors, exploiting the opportunities of high density microelectronic technologies and the great progress made in recent years by vertical interconnection processes. Today it is possible to fabricate three-dimensional (“3D”) integrated circuits, which allow the microelectronic industry to increase the integration density and to deal effectively with a major problem of scaled CMOS processes, that is, the length of the interconnections. Moreover, the various layers of the integrated circuit can be designed according to different criteria, depending on the specific application (analog layer, digital layer, sensor layer). A vertical integration technology makes it possible to design a tracking system which overcomes the intrinsic limitations of present hybrid pixel sensors and of CMOS MAPS (Monolithic Active Pixel Sensors). With respect to MAPS, the vertical integration of sensor and readout electronics makes it possible to use a fully-depleted high resistivity silicon substrate for particle detection, providing a large benefit in terms of radiation hardness and signal-to-noise ratio. A possible alternative may preserve the classical MAPS concept of signal charge generation and collection by diffusion in an undepleted silicon region; in this case vertical integration make it possible to separate the analog front-end electronics from the digital readout sections, with great advantages in terms of pixel pitch, functionalities and performance. Vertical integration also gives the opportunity to fabricate thin MAPS stacks, implementing an integrated multilayer sensor with high resolution in trajectory and momentum measurements. With respect to present hybrid pixels, vertical integration opens up solutions to problems such as the excessive amount of material and the relative large pitch of present systems, which are based on bump bonding techniques between readout integrated circuits and “2D” sensors. The background of the VIPIX project consists in the results reached by the participating units in INFN projects (SLIM5, SHARPS, DIGIMAPS, P-ILC) which led to the development of devices and systems in subquartermicron CMOS technologies. The proposal of a research program on a vertically integrated pixel system is today based on the availability of commercial technologies at relatively low cost. Besides the development of sensors and front-end electronics, VIPIX plans to tackle the system issue connected to an optimal operation of these devices. This includes the investigation of technologies for the mechanical support and the cooling system, including the possible use of microchannels built in the silicon substrate with micromachining techniques. Moreover, VIPIX will pursue the possibility of using associative memories in the DAQ system, for the online track reconstruction and the interfacing with a Level 1 Trigger system. Updating the infrastructure developed in SLIM5, the VIPIX vertically integrated pixels will be tested in a beam. The ultimate goal of the VIPIX project is to advance the state of the art of MAPS and hybrid pixel systems in terms of both functionality and performance.